Method of reading a capacitive sensor and related integrated circuit

ABSTRACT

The method is for reading a capacitive sensor and may be implemented by a circuit for biasing and reading capacitances that includes circuits for selecting a column line and a row line, and a charge amplifier producing an output voltage representing the capacitance of the selected capacitor intercepted by the selected column and row lines. The method includes preliminarily resetting the output voltage of the charge amplifier, connecting all the deselected row and column plates of the array to a reference voltage and connecting a feedback capacitor and the selected capacitor to an inverting input of the amplifier, applying a step voltage on the capacitor that is connected to the inverting input of the amplifier, and reading the output voltage at steady-state.

FIELD OF THE INVENTION

[0001] The present invention relates to the field of capacitive sensors, and more particularly to methods and integrated systems for reading a plurality of capacitors of a capacitive sensor including an array of capacitors.

BACKGROUND OF THE INVENTION

[0002] Capacitive sensors are largely used as contact or pressure sensors. According to a particular embodiment, they may comprise an array of capacitors ordered in rows and columns connected through row and column lines (or plates), as schematically depicted in FIG. 1. These sensors produce a distribution map of the pressure even on a relatively large surface. The capacitance of each single capacitor of these sensors depends on the degree of deformation undergone by the dielectric layer of the capacitor, induced by a compressive force exerted thereon. By reading the values of the capacitances of all the capacitors of the array, an “array” of values (“frame”) describing the spatial distribution of the pressure field on the sensing surface of the sensor is obtained.

[0003] The pressure field on the sensing surface may be easily displayed by a gray scale image, in which the luminance of each pixel is a function of the measured capacitance of a corresponding capacitor of the array.

[0004] Several problems have so far prevented realization of relatively low cost systems for reading such capacitive pressure sensors with good precision and with a great flexibility of use such to make them usable in particularly demanding applications. The precision of the sensing (reading) system of these sensors is negatively affected by the fact that the reading of the capacitance of a capacitor of the array is disturbed by the presence of the other capacitors and by parasitic capacitances between adjacent rows and columns. The capacitances affecting the reading of a single capacitor may add up to be 2 or 3 orders of magnitude greater than the capacitance of the selected capacitor being read to be detected. Moreover, a truly multipurpose system suitable to be used in many types of applications should work properly even if it is necessary to vary from time to time the number of addressable rows and columns of the array, depending on the particular application.

SUMMARY OF THE INVENTION

[0005] It is an object of the present invention to provide a method and a system for reading a capacitive sensor that overcomes the above mentioned problems. The system of the invention can be realized in monolithic form and at a relatively low cost and may be used with sensors of different numbers of rows and columns.

[0006] More precisely the invention includes a method for reading a capacitive sensor formed by an array of capacitors ordered in rows and columns functionally connected through row lines, each one electrically constituting a first plate in common to all the capacitors of a row, and through column lines, each one electrically constituting a second plate in common to all the capacitors of a column; the two sets of plates being orthogonal or quasi-orthogonal to each other. The method of the invention may be implemented by a circuit for biasing and reading capacitances that includes circuits for selecting a column line and a row line, and a charge amplifier producing an output voltage representing the capacitance of the selected capacitor intercepted by the selected column and row lines.

[0007] The method includes preliminarily resetting the output voltage of the charge amplifier, connecting to a reference voltage all the deselected row and column plates of the array and connecting an auxiliary capacitor and the selected capacitor to an inverting input of the amplifier and as feedback capacitor of the amplifier, respectively, or vice versa, and applying a step voltage on the capacitor that is connected to the inverting input of the amplifier and reading the output voltage at steady-state.

[0008] The reading method of the invention contemplates the scanning of all the capacitors of the array, to obtain as many values of capacitances. This “array” of values may be periodically updated at a certain “frame frequency”, to display the way the distribution map of the pressure on the sensor area evolves in time.

[0009] The integrated reading system for a capacitive sensor of the invention comprises an input interface circuit connected to the capacitive sensor, forcing to a reference potential all deselected row plates and the column plates of the array and coupling to a biasing and reading circuit of the system the selected capacitor intercepted by the selected row and the selected column. The system also includes a biasing and reading circuit, producing an output voltage representative of the capacitance of the selected capacitor coupled thereto; an analog-to-digital converter in cascade of the biasing and reading circuit converting the representative voltage in a corresponding bit vector; a microprocessor unit controlling the functioning of the system; and an output interface circuit functionally coupled to the microprocessor unit, outputting the read values of capacitance.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The different aspects and advantages of the invention will become even more evident through the following detailed description of several embodiments and by referring to the attached drawings, wherein:

[0011]FIG. 1 is a schematic diagram depicting the array of capacitors of a capacitive sensor;

[0012]FIG. 2 is a functional diagram of the integrated system of the invention according to a preferred embodiment;

[0013]FIG. 3 is a detailed diagram of the input interface of the system of the invention;

[0014]FIG. 4 is a schematic diagram showing a biasing and reading circuit according to a first embodiment of the invention;

[0015]FIG. 5 is a schematic diagram showing a biasing and reading circuit according to another embodiment of the invention;

[0016]FIG. 6 is a schematic diagram shows a preferred embodiment of the biasing and reading circuit suited to implement any of the two different embodiments of the method of the invention;

[0017]FIG. 7 is a functional diagram of the input interface circuit;

[0018]FIG. 8 is a schematic diagram showing an embodiment of the circuit for coupling the selected capacitor to be read to the biasing and reading circuit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] A preferred embodiment of the system of the invention, that may be readily integrated, is depicted in FIG. 2, in the form of block diagram. It includes an input interface block ANAIO, a biasing and reading block READOUT, an analog to digital conversion block ADC, a control block COMPUTING CORE and an output digital interface DIGITALI/O. In practice, the input interface ANAIO couples the selected capacitor C_(PIX) to be read to the biasing and reading circuit READOUT producing a voltage signal V_(o) representative of the capacitance of the read capacitor and grounds the plates of substantially all deselected capacitors of the sensor array. An analog-to-digital converter ADC converts the analog voltage V₀ in a corresponding multibit datum of bit vector.

[0020] The processing and control function are executed via an internal bus INTERNAL PERIPHERAL BUS by a control block COMPUTING CORE that comprises a microprocessor unit μP, ROM, RAM and BRIDGE. The control may also optionally and preferably involve a waveform generator WAVEFORM GENERATOR. This generator WAVEFORM GENERATOR that is controlled by the microprocessor unit, generates the signals for synchronizing the various functioning phases of the circuit READOUT and of the analog-to-digital conversion circuit ADC of the voltage V_(o). The use of a dedicated generator WAVEFORM GENERATOR is particularly convenient, because it facilitates the programming of an optimized generation of such timing signals. A suitable waveform generator can be easily implemented by employing a ring register that is configured by a finite states machine controlled by the microprocessor unit, as will be readily recognized by a skilled technician.

[0021] The actual connections of input interface block are stage is depicted in a greater detail in FIG. 3. The interface ANAIO is connected to the capacitive array sensor through a plurality of pins of the chip, for coupling the selected row and column plates (lines) of capacitors of the sensor to the circuit READOUT.

[0022] Two alternative embodiments of the system of the invention are exemplified in FIGS. 4 and 5. Both employ a charge amplifier that represents the sensing element of the READOUT block. The charge amplifier is constituted by an operational amplifier with a non inverting input (+) connected to a ground potential and an inverting input (−) that is coupled to the capacitor to be read and to a feedback capacitor.

[0023] According to the embodiment depicted in FIG. 4, the selected capacitor C_(PIX) to be read is coupled to the input (−) of the operational amplifier, while the feedback capacitor C_(R) is a conventionally connected and is dischargeable by the shortcircuiting switch S1.

[0024] The method of reading the capacitance of C_(PIX) includes:

[0025] (a) resetting the voltage V_(o) by momentarily closing the switch S1;

[0026] (b) connecting the selected row and column plates to a reference potential;

[0027] (c) applying a step voltage V_(I) to the selected capacitor C_(PIX) connected to the input (−) of the amplifier, sensing at steady-state the voltage V_(o).

[0028] In this way, the voltage V_(o) is subject to a variation ΔV_(O) proportional to the variation ΔV_(I) of the voltage V_(I), according to the following formula: ${\Delta \quad V_{O}} = {\Delta \quad {V_{I} \cdot \frac{C_{PIX}}{C_{R}}}}$

[0029] The charge injection into the feedback capacitor C_(R), by the neighboring capacitors of the selected capacitor and by the parasitic capacitances C_(COL) and C_(ROW), is effectively nullified because all deselected rows and columns are grounded.

[0030] According to an alternative embodiment, depicted in FIG. 5, connection of the selected capacitor Cpix and of the feedback capacitor Cr may be inverted by connecting the selected capacitor C_(PIX) to be read as feedback capacitor and by connecting the auxiliary capacitor C_(R) to the input (−) of the amplifier. According to this alternative embodiment of the biasing and sensing circuit there will be a variation of the output voltage ΔV_(O) given by ${\Delta \quad V_{O}} = {\Delta \quad {V_{I} \cdot \frac{C_{R}}{C_{PIX}}}}$

[0031] that is the output voltage presents a variation that, differently from the first embodiment, is inversely proportional to the selected capacitance C_(PIX).

[0032] The two alternative configurations of FIGS. 4 and 5 may be implemented with the same integrated circuit as the one depicted in FIG. 6, in which, by acting on the configuration switches controlled by a logic signal FEEDBACK, the selected capacitor to be read C_(PIX) may be coupled to the input and the auxiliary capacitor C_(R) connected as feedback capacitor to the charge amplifier or viceversa.

[0033] To make the input interface ANAIO suited to support array sensors of different number of rows and columns, it is realized, as depicted in FIG. 7, by a plurality of identical connection modules ANAIOCIRCUIT, each connected to a respective pin that are controlled by a dedicated selection logic ANAIOCONTROL. Each connection module ANAIOCIRCUIT, that may be realized as depicted in FIG. 8, connects a respective row or column of the sensor array to a reference potential or to the biasing and reading circuit READOUT, in function of selection signals ISIN, SELTHIS that are generated by a selection logic circuit controlled by the microprocessor unit.

[0034] A monolithically integrated system of the invention with such a modular input interface circuit, may be used with capacitive sensors having any number of rows and columns of capacitors, provided that the sum of the number of rows and columns does not exceed the number of input channels (modules) of the input interface. In the case the modules of the input interface of the device are more numerous than the sum of rows and columns of the array of capacitors of the sensor to be used, the redundant connection circuits that are not used for coupling a respective row or column connect the respective pin of the device to a reference potential, as if they were connected to deselected rows or columns, without affecting the normal functioning of the integrated system.

[0035] Naturally, the method of the invention can be implemented by sequentially scanning the capacitors of the array for producing an array of values representing the map distribution of the quantity (pressure) detected by the capacitive sensor. Such a sequential scan may be repeated with a desired frequency (“frame frequency”) for continuously refreshing the image of the distribution map of the pressure on the sensing area of the sensor.

[0036] Each frame of values so produced may be subjected by the microprocessor unit to noise filtering and to appropriate real-time correction processes such as the “gamma correction” and the “fixed pattern noise cancellation”, before being output through a conventional digital output interface DIGITALI/O. To these purposes, the microprocessor unit will include a RAM of sufficient capacity for storing calculated capacitance values, besides a conventional ROM for storing information relating system's configuration and to the communication protocol employed. 

That which is claimed is:
 1. A method of reading a capacitive sensor constituted by an array of capacitors ordered in rows and columns functionally connected through row lines, each electrically constituting a first plate of all the capacitors of a row, and through column lines, each electrically constituting a second plate of all the capacitors of a column, orthogonal or quasi-orthogonal to each other, using a biasing and reading circuit (READOUT) comprising column and row selectors, a charge amplifier outputting a voltage (V_(o)) function of the capacitance of a selected capacitor (C_(PIX)) of said array, comprising the steps of: preliminarily resetting the output voltage (V_(o)) of said charge amplifier; connecting to a reference voltage all the deselected row and column plates of said array and connecting an auxiliary capacitor (C_(R)) and said selected capacitor (Cpix) to an inverting input (−) of the amplifier and as feedback capacitor of said amplifier, respectively, or viceversa; applying a step voltage (V_(I)) on the capacitor (C_(R), C_(PIX)) that is connected to the inverting input (−) of the amplifier and reading at steady-state, said output voltage (V_(o)).
 2. The method of claim 1, wherein the reading of the sensor includes a sequential scanning of the capacitors of the array, obtaining a frame of as many values of capacitance of the sensor.
 3. The method of claim 2, wherein the scan is repeated with a certain frame frequency.
 4. An integrated system for reading a capacitive sensor constituted by an array of capacitors ordered in rows and columns functionally connected through row lines, each electrically constituting a first plate of all the capacitors of a row, and through column lines, each electrically constituting a second plate of all the capacitors of a column, orthogonal or quasi-orthogonal to each other, comprising: an input interface circuit (ANAIO) for coupling therethrough said capacitive sensor, the interface circuit grounding deselected row plates and column plates of said array and connecting a single capacitor (C_(PIX)) at the time selected by row and column selectors; a biasing and reading circuit (READOUT) composed of a charge amplifier outputting said voltage (V_(o)) function of the capacitance of the selected capacitor (C_(PIX)), having an inverting input (−), a feedback capacitor and a reset switch (S1), configuration switches for coupling said auxiliary capacitor (C_(R)) and said selected capacitor (Cpix) as feedback capacitor and to said input of the amplifier, respectively or viceversa; an analog-to-digital converter (ADC) converting said output voltage (V_(o)) in a corresponding multibit datum; a processing and controlling microprocessor unit (COMPUTING CORE) performing noise filtering and real-time correction of data; a digital output interface circuit (DIGITALI/O) controlled by said microprocessor unit for outputting the data of the read values of capacitance of the sensor.
 5. The system according to claim 4, further comprising a timing signal generator (WAVEFORM GENERATOR), controlled by said microprocessor unit, generating timing signals for said row and column selectors, for the biasing and reading circuit (READOUT) and for the converter (ADC), for synchronizing the operation phases of the circuits.
 6. The system of claim 5, wherein said waveform generator (WAVEFORM GENERATOR) is composed of a a shift register cyclically producing said timing signals with a certain frequency; a finite state machine, controlled by the microprocessor unit, for configuring said shift register.
 7. The system according to any of claims from 4 to 6, wherein said input interface circuit (ANAIO) comprises a plurality of identical connection modules (ANAIOCIRCUIT) for grounding the deselected row plates and the deselected column plates, and coupling to said biasing and reading circuit (READOUT) the selected capacitor (C_(PIX)) , in function of selection signals (ISIN, SELTHIS); a selection logic circuit (ANAIOCONTROL) controlled by said microprocessor unit (COMPUTING CORE) producing said selection signals (ISIN, SELTHIS). 